They will also affect the way Verilog code is written and implemented. Certain RTL coding style can cause simulation vs synthesis mismatch and care has to be taken to avoid those. The code is written using only the synthesizable constructs of Verilog. The Verilog code is then given for Verification and the fully verified code is given for physical implementation. The code here more closely resembles generic software structures like for/while/do loops etc.ĭesign involves implementing the specification of a circuit generally at the RTL level of abstraction.
The code written in this use case need not be synthesizable and it remains within verification sphere. In this use case, the primary aim is to generate test vectors to validate the design as per the specification. The precise steps and sequences vary based on the exact nature of implementation. R1 placement -> clock tree construction -> routing -> DRC -> LVS -> to tapeout. The inherent simultaneous operations in the physical chip is mimicked in the language by always (most commmon), initial and fork/join blocks. There is always a "module" at the top-level representing the chip structure (for synthesis), and one at the system level for verification. The number of entities and interconnects do not change dynamically. Modules (module), Ports(input/output/inout), connections (wires), blocks registers (reg) are all fixed at compile time. Its structure and main principles ( as described below ) are designed to describe and successfully implement an electronic system.Īn electronic circuit is a physical entity having a fixed structure and Verilog is adapted for that. It is also used in the verification of analog circuits and mixed-signal circuits. It most commonly describes an electronic system at the register-transfer level (RTL) of abstraction. Verilog is a hardware description language (HDL) used to model electronic systems.
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